Design and Optimized Implementation of Six-Operand Single- Precision Floating-Point Addition
نویسندگان
چکیده
In this paper we present an efficient design of generalized, multi-operand single-precision floating point addition. The addition operation is optimized in two ways. Firstly, the design of [4] has been modified to improve efficiency of multi-operand floating point addition in terms of speed and area. Secondly, varieties of adders were analyzed for parallel addition and identified suitable adder. Our approach is applied to six operand floating point addition to compare with the related works. The implementation is synthesized and verified on Xilinx Virtex4 FPGA. Further, the performance of proposed design was compared in terms of speed and resources with other designs, the comparison results are also presented in this paper.
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